1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a manufacturing method thereof and, more particularly, to a nonvolatile semiconductor memory and a manufacturing method thereof using a nonvolatile memory cell formed by stacking a charge storage layer and control gate electrode.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) in which data write and erase are electrically performed is conventionally known as a semiconductor memory. Also, a NAND flash memory that can be highly integrated is known as one EEPROM.
A memory cell transistor of the NAND flash memory has a laminated gate structure in which a floating gate electrode for storing electric charge, an inter-gate insulating film, and a control gate electrode are stacked on a tunnel insulating film on a semiconductor substrate.
Micropatterning of the memory cell transistors of the NAND flash memories is rapidly advancing, and the inter-cell interference is an example of the characteristics that make this micropatterning difficult. When writing data in a memory cell transistor of interest and then writing data in a memory cell transistor adjacent to the cell of interest, the potential of the floating gate electrode of the cell of interest fluctuates under the influence of the potential of the floating gate electrode (or the amount of electric charge injected in the floating gate electrode) of the adjacent cell. The inter-cell interference is the characteristic that the data written in the cell of interest changes owing to this potential fluctuation.
The influence of the change in written data on the device characteristics increases as the number of levels of data to be written in one memory cell transistor increases and the distance between the floating gate electrodes decreases. Increasing the number of levels of data is an essential characteristic of the NAND flash memory whose advantage is a high density. To suppress the inter-cell interference, therefore, it is possible to decrease the parasitic capacitance of the floating gate electrode by decreasing its film thickness.
Decreasing the film thickness of the floating gate electrode has the merit that the inter-cell interference is suppressed. On the other hand, it is necessary to short-circuit the control gate electrodes and floating gate electrodes of the gate electrodes of two selection gate transistors arranged at the two ends of a memory cell string (formed by connecting a plurality of memory cell transistors in series). If the film thickness of the floating gate electrode is decreased, therefore, the margin of a short circuit between the floating gate electrode and semiconductor substrate decreases, and this decreases the yield.
As a related technique of this kind, a technique is disclosed that suppresses crystal defects of a semiconductor substrate caused by expansion of an element isolation insulating film by forming a silicon nitride layer on the inner walls of an element isolation trench, thereby improving the electrical characteristics and reliability of a nonvolatile semiconductor memory (Jpn. Pat. Appln. KOKAI Publication No. 2002-252291 [corresponding U.S. Pat. No. 6,580,117]).